Field Programmable Logic and Applications : 9th International Workshop, FPL’99, Glasgow, UK, August 30 - September 1, 1999. Proceedings - Lysaght, Patrick; Irvine, James; Hartenstein, Reiner; SpringerLink (Online service) (Berlin, Heidelberg : Springer Berlin Heidelberg, 1999)
This book contains the papers presented at the 9th International Workshop on Field ProgrammableLogic and Applications (FPL’99), hosted by the University of Strathclyde in Glasgow, Scotland, August 30 – September 1, 1999. FPL’99 is the ninth in the series of annual FPL workshops. The FPL’99 programme committee has been fortunate to have received a large number of high-quality papers addressing a wide range of topics. From these, 33 papers have been selected for presentation at the workshop and a further 32 papers have been accepted for the poster sessions. A total of 65 papers from 20 countries are included in this volume. FPL is a subject area that attracts researchers from both electronic engine- ing and computer science. Whether we are engaged in research into soft ha- ware or hard software seems to be primarily a question of perspective. What is unquestionable is that the interaction of groups of researchers from di?erent backgrounds results in stimulating and productive research. As we prepare for the new millennium, the premier European forum for - searchers in ?eld programmable logic remains the FPL workshop. Next year the FPL series of workshopswill celebrate its tenth anniversary.The contribution of so many overseas researchers has been a particularly attractive feature of these events, giving them a truly international perspective, while the informal and convivial atmosphere that pervades the workshops have been their hallmark. We look forward to preserving these features in the future while continuing to expand the size and quality of the events.
Signal Processing -- Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing -- Auditory Signal Processing in Hardware -- SONIC – A Plug-In Architecture for Video Processing -- CAD Tools for DRL -- DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems -- Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework -- Optimization Studies -- Optimal Finite Field Multipliers for FPGAs -- Memory Access Optimization and RAM Inference for Pipeline Vectorization -- Analysis and Optimization of 3-D FPGA Design Parameters -- Physical Design -- Tabu Search: Ultra-Fast Placement for FPGAs -- Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies -- Hierarchical Interactive Approach to Partition Large Designs into FPGAs -- Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays -- Dynamically Reconfigurable Logic -- DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems -- A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic -- Self Controlling Dynamic Reconfiguration: A Case Study -- Design Tools -- An Internet Based Development Framework for Reconfigurable Computing -- On Tool Integration in High-Performance FPGA Design Flows -- Hardware-Software Codesign for Dynamically Reconfigurable Architectures -- Reconfigurable Computing -- Serial Hardware Libraries for Reconfigurable Designs -- Reconfigurable Computing in Remote and Harsh Environments -- Communication Synthesis for Reconfigurable Embedded Systems -- Run-Time Parameterizable Cores -- Applications -- Rendering PostScript TM Fonts on FPGAs -- Implementing PhotoShopTM Filters in VirtexTM -- Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler -- Quantitative Analysis of Run-Time Reconfigurable Database Search -- Novel Architectures -- An On-Line Arithmetic Based FPGA for Low-Power Custom Computing -- A New Switch Block for Segmented FPGAs -- PulseDSP – A Signal Processing Oriented Programmable Architecture -- Machine Applications -- FPGA Viruses -- Genetic Programming Using Self-Reconfigurable FPGAs -- Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs -- Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs -- Short Papers -- An FPGA-Based Prototyping System for Real-Time Verification of Video Processing Schemes -- An FPGA Implementation of Goertzel Algorithm -- Pipelined Multipliers and FPGA Architectures -- FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding -- Reconfigurable Multiplier for Virtex FPGA Family -- Pipelined Floating Point Arithmetic Optimised for FPGA Architectures -- SL – A Structural Hardware Design Language -- High-Level Hierarchical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules -- Mapping Applications onto Reconfigurable KressArrays -- Global Routing Models -- Power Modelling in Field Programmable Gate Arrays (FPGA) -- NEBULA: A Partially and Dynamically Reconfigurable Architecture -- High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects -- AHA-GRAPE: Adaptive Hydrodynamic Architecture – GRAvity PipE -- DIME – The First Module Standard for FPGA Based High Performance Computing -- The Proteus Processor — A Conventional CPU with Reconfigurable Functionality -- Logic Circuit Speeding up through Multiplexing -- A Wildcarding Mechanism for Acceleration of Partial Configurations -- Hardware Implementation Techniques for Recursive Calls and Loops -- A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation -- An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis -- Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array’s: An Integrated Approach Based on Reconfigurable Virtual Architectures -- A Concept for an Evaluation Framework for Reconfigurable Systems -- Debugging Application-Specific Programmable Products -- IP Validation for FPGAs Using Hardware Object TechnologyTM -- A Processor for Artificial Life Simulation -- A Distributed, Scalable, Multi-layered Approach to Evolvable System Design Using FPGA’s -- Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching -- A Reconfigurable Architecture for High Speed Computation by Pipeline Processing -- Seeking (the Right) Problems for the Solutions of Reconfigurable Computing -- A Runtime Reconfigurable Implementation of the GSAT Algorithm -- Accelerating Boolean Implications with FPGAs.
SpringerLink.
Keywords: Computer science; Arithmetic and logic units, Computer; Logic design; Microprocessors; Architecture, Computer; Complexity, Computational; Computer Science; Computer System Implementation; Logic Design; Arithmetic and Logic Structures; Processor Architectures; Complexity